3D active edge silicon sensors: Device processing, yield and QA for the ATLAS-IBL production

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R&D Paths of Pixel Detectors for Vertex Tracking and Radiation Imaging

This report reviews current trends in the R&D of semiconductor pixellated sensors for vertex tracking and radiation imaging. It identifies requirements of future HEP experiments at colliders, needed technological breakthroughs and highlights the relation to radiation detection and imaging applications in other fields of science.Comment: 17 pages, 2 figures, submitted to the European Strategy Preparatory Grou

MEMS sensors and Vertically Integrated Micro-Fabricated Systems

The aim of this addendum is to answer the questions raised by the LHCC committee

Thin pixel development for the superB silicon vertex tracker

The high luminosity SuperB asymmetric e+ e− collider, to be built near the INFN National Frascati Laboratory in Italy, has been designed to deliver a luminosity greater than 10^36 cm−2 s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10–15um in both coordinates, low material budget (<1% X0), and able to withstand a background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device with these stringent requirements is being pursued with specific R&D programs on different technologies: hybrid pixels, CMOS MAPS and pixel sensors developed with vertical integration technology. The latest results on the various pixel options for the SuperB SVT will be presented

The front-end chip of the SuperB SVT detector

The asymmetric e(+) e(-) collider SuperB is designed to deliver a high luminosity, greater than 10(36) cm(-2) S-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%

Advances in the development of pixel detector for the SuperB Silicon Vertex Tracker

The latest advances in the design and characterization of several pixel sensors developed to satisfy the very demanding requirements of the innermost layer of the SuperB Silicon Vertex Tracker will be presented in this paper. The SuperB machine is an electron positron collider operating at the ϒ(4S)ϒ(4S) peak to be built in the very near future by the Cabibbo Lab consortium. A pixel detector based on extremely thin, radiation hard devices able to cope with rate in the tens of MHz/cm^2 range will be the optimal solution for the upgrade of the inner layer of the SuperB tracking system. At present several options with different levels of maturity are being investigated to understand advantages and potential issues of the different technologies: thin hybrid pixels, Deep N-Well CMOS MAPS, INMAPS CMOS MAPS featuring a quadruple well and high resistivity substrates and CMOS MAPS realized with Vertical Integration technology. The newest results from beam test, the outcomes of the radiation damage studies and the laboratory characterization of the latest prototypes will be reported